This invention relates generally to non-volatile memory devices, and more particularly to a non-volatile memory device comprised of an array of vertical field effect transistor structures as flash memory cells with each vertical field effect transistor fabricated by growing a semiconductor material within an opening formed through doped insulating materials for defining the drain and source extension junctions of the vertical field effect transistor and through a layer of dummy material deposited between the doped insulating materials for defining the channel region of the vertical field effect transistor.
A non-volatile memory device is comprised of an array of flash memory cells with each flash memory cell storing 1-bit of digital information, as known to one of ordinary skill in the art of electronics. Referring to FIG. 1, a flash memory cell 100 of a prior art non-volatile memory device includes a tunnel gate dielectric 102 comprised of silicon dioxide (SiO2) for example as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel gate dielectric 102 is disposed on a semiconductor substrate 103. In addition, a floating gate electrode 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel gate dielectric 102. A control gate dielectric 106, comprised of silicon dioxide (SiO2) for example as known to one of ordinary skill in the art of integrated circuit fabrication, is disposed over the floating gate electrode 104. A control gate electrode 108, comprised of a conductive material such as polysilicon for example, is disposed over the control gate dielectric 106.
A drain junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate 103 toward a left sidewall of the floating gate electrode 104 in FIG. 1. A source junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate 106 toward a right sidewall of the floating gate electrode 104 of FIG. 1. The active device area 112 of the semiconductor substrate 103 is defined by shallow trench isolation structures 116 that electrically isolate the flash memory cell 100 from other integrated circuit devices within the semiconductor substrate 103.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or injected out of the floating gate electrode 104 through the tunnel gate dielectric 102. Such variation of the amount of charge carriers within the floating gate electrode 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of electronics. For example, when electrons are the charge carriers that are injected into the floating gate electrode 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the floating gate electrode 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate electrode 108, a voltage of +5 Volts is applied on the drain junction 110, and a voltage of 0 Volts (or a small bias of 0.25 Volts for example) is applied on the source junction 114 and on the semiconductor substrate 103. Alternatively, during erasing of the flash memory cell 100, referring to FIG. 2, a voltage of xe2x88x929.5 Volts is applied on the control gate electrode 108, a voltage of 0 Volts is applied on the drain junction 110, and a voltage of +4.5 Volts is applied on the source junction 114 and on the semiconductor substrate 103. Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.
Referring to FIG. 3, an alternative flash memory cell 150 is comprised of a charge storing gate dielectric stack 120 between the control gate electrode 108 and the semiconductor substrate 103. Elements having the same reference number in FIGS. 1, 2, and 3 refer to elements having similar structure and function. The charge storing gate dielectric stack 120 is comprised of a tunnel gate dielectric 120 formed on the semiconductor substrate 103, a charge storing dielectric 122 formed on the tunnel gate dielectric 120, and a control gate dielectric 124 formed on the charge storing dielectric 122.
In one example of the charge storing gate dielectric stack 120, the tunnel gate dielectric 120 is comprise of silicon dioxide (SiO2) having a thickness of about 100 angstroms, the charge storing dielectric 122 is comprised of silicon nitride (Si3N4) having a thickness of about 85 angstroms, and the control gate dielectric 124 is comprised of silicon dioxide (SiO2) having a thickness of about 100 angstroms, formed in an ONO (oxide-nitride-oxide) deposition process as known to one of ordinary skill in the art of integrated circuit fabrication. During the program or erase operations of the flash memory cell 150 of FIG. 3, charge carriers are injected into or injected out of the charge storing dielectric 122 through the tunnel gate dielectric 120. Such variation of the amount of charge carriers within the charge storing dielectric 122 alters the threshold voltage of the flash memory cell 150, as known to one of ordinary skill in the art of electronics.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
In the flash memory cell 100 or 150 of FIGS. 1, 2, and 3, as the dimensions including the length of the channel region between the drain 110 and the source 114 of the flash memory cell 100 or 150 are further scaled down to tens of nanometers, short-channel effects degrade the performance of the flash memory cell 100 or 150. Short-channel effects that result due to the short length of the channel region between the drain junction 104 and the source junction 106 of the flash memory cell 100 or 150 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the flash memory cell 100 or 150 become difficult to control with short-channel effects which may severely degrade the performance of the flash memory cell 100 or 150.
In the conventional planar flash memory cell 100 or 150 of FIGS. 1, 2 and 3, the gate stack (comprised of the tunnel gate dielectric 102, the floating gate electrode 104, the control gate dielectric 106, and the control gate electrode 108 for the flash memory cell 100, or comprised of the charge storing gate dielectric stack 120, 122, and 124 and the control gate electrode 108 for the flash memory cell 150) is disposed over one plane of the channel region between the drain and source junctions 110 and 114. However, as the dimensions of the flash memory cell 100 or 150 are further scaled down to tens of nanometers, control of charge accumulation within the channel region of the flash memory cell 100 or 150 from a plurality of planes of the channel region is desired to minimize short channel effects.
Accordingly, the present invention is directed to fabrication of an array of flash memory cells for a non-volatile memory device with each flash memory cell of the array being comprised of a vertical field effect transistor structure having a gate stack formed at each of a plurality of planes of the channel region of the vertical field effect transistor to minimize undesired short channel effects.
In a general aspect of the present invention, for fabricating each vertical field effect transistor as a flash memory cell of the non-volatile memory device, a first drain or source contact structure comprised of a semiconductor material is formed to be surrounded by shallow trench isolation structures. The first drain or source contact structure is doped with a first dopant. A bottom layer of doped insulating material is deposited on the first drain or source contact structure, and the bottom layer of doped insulating material is doped with a second dopant. A layer of dummy material is deposited on the bottom layer of doped insulating material. A top layer of doped insulating material is deposited on the layer of dummy material, and the top layer of doped insulating material is doped with a third dopant.
An opening is etched through the top layer of doped insulating material, the layer of dummy material, and the bottom layer of doped insulating material. The opening is disposed over the first drain or source contact structure such that the opening has a bottom wall of the semiconductor material of the first drain or source contact structure. The opening is filled with a semiconductor material to form a semiconductor fill contained within the opening. The semiconductor fill has at least one side wall with a top portion of the at least one sidewall abutting the top layer of doped insulating material, and with a middle portion of the at least one sidewall abutting the layer of dummy material, and with a bottom portion of the at least one sidewall abutting the bottom layer of doped insulating material.
A fourth dopant is implanted into a top surface of the semiconductor fill to form a second drain or source contact junction of the vertical field effect transistor. The layer of dummy material is etched away such that the middle portion of the at least one sidewall of the semiconductor fill is exposed. A gate electrode opening disposed between the top and bottom layers of doped insulating material is formed when the layer of dummy material is etched away. A tunnel gate dielectric of the vertical field effect transistor is formed on the exposed middle portion of the at least one side wall of the semiconductor fill. The middle portion of the semiconductor fill abutting the tunnel gate dielectric forms a channel region of the vertical field effect transistor.
The gate electrode opening between the top and bottom layers of doped insulating material is filled with a floating gate electrode material, and the floating gate electrode material abuts the tunnel gate dielectric to form a floating gate electrode of the vertical field effect transistor. The tunnel gate dielectric and the floating gate electrode formed at the at least one side wall of the semiconductor fill are disposed on a plurality of planes of the channel region of the vertical field effect transistor. A thermal anneal is performed such that the second dopant diffuses from the bottom layer of doped insulating material into the bottom portion of the semiconductor fill to form a first drain or source extension junction of the vertical field effect transistor, and such that the third dopant diffuses from the top layer of doped insulating material into the top portion of the semiconductor fill to form a second drain or source extension junction of the vertical field effect transistor.
A control gate dielectric material is deposited on any exposed surfaces of the floating gate electrode of the vertical field effect transistor to form a control gate dielectric on the floating gate electrode. In addition, a control gate electrode material is deposited on the control gate dielectric material to form a control gate electrode on the control gate dielectric. The control gate electrode material is patterned to be continuous for a row of the array of flash memory cells such that the control gate electrode of each vertical field effect transistor of the row of flash memory cells is coupled together to form a word line of the non-volatile memory device.
Furthermore, the semiconductor fill is patterned to be continuous for a column of the array of flash memory cells such that the second drain or source contact junction of each vertical field effect transistor of the column of flash memory cells is coupled together to form a bit line of the non-volatile memory device when the first drain or source contact structure of each vertical field effect transistor of the column of flash memory cells is electrically isolated. Alternatively, the first drain or source contact structure is patterned to be continuous for a column of flash memory cells such that the first drain or source contact structure of each vertical field effect transistor of the column of flash memory cells is coupled together to form a bit line of the non-volatile memory device when the second drain or source contact junction of the semiconductor fill of each vertical field effect transistor of the column of flash memory cells is electrically isolated.
In one embodiment of the present invention, the bottom and top layers of the doped insulating material are comprised of PSG (phospho-silicate glass) such that the second and third dopants are comprised of phosphorous for formation of a vertical NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) for each flash memory cell. In an alternative embodiment of the present invention, the bottom and top layers of the doped insulating material are comprised of BSG (boro-silicate glass) such that the second and third dopants are comprised of boron for formation of a vertical PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) for each flash memory cell.
In another embodiment of the present invention, the vertical field effect transistor for each flash memory cell is formed with a charge storing gate dielectric stack on the exposed middle portion of the at least one sidewall of the semiconductor fill and with the control gate electrode material on the charge storing gate dielectric stack. In that case the floating gate electrode is not formed.
In a further embodiment of the present invention, a logic field effect transistor is fabricated on a peripheral region of the semiconductor substrate simultaneously with fabrication of the vertical field effect transistor for each flash memory cell of the non-volatile memory device. The gate electrode of the logic field effect transistor in the peripheral region is formed from the control gate electrode material comprising the control gate electrode of the vertical field effect transistor for the flash memory cell.
In this manner, a vertical field effect transistor structure is formed for each flash memory cell of the non-volatile memory device to have a tunnel gate dielectric and a floating gate electrode on each of a plurality of planes of the channel region formed within the semiconductor fill for better control of charge accumulation within the channel region such that undesired short channel effects are minimized. In addition, with application of bias voltage on the control gate electrode at each of a plurality of planes of the channel region, higher drive current is achieved for enhanced speed performance of the vertical field effect transistor. Furthermore, the length of the channel region is determined by the thickness of the layer of dummy material deposited between the top and bottom layers of doped insulating material. Thus, the length of the channel region of the vertical field effect transistor may be scaled down beyond those possible from photolithography limitations. Additionally, because the drain, source, and the channel region extends upward from the semiconductor substrate for the vertical field effect transistor, such a vertical field effect transistor may occupy a smaller area of the semiconductor substrate such that a compact array of flash memory cells is formed for the non-volatile memory device.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.